1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to improved routing architectures for a programmable logic device.
2. Description of the Related Art
A programmable logic device (xe2x80x9cPLDxe2x80x9d) is a digital, user-configurable integrated circuit used to implement a custom logic function. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by the end-user, and includes a programmable logic array (xe2x80x9cPLAxe2x80x9d), a field programmable gate array (xe2x80x9cFPGAxe2x80x9d), and an erasable and complex PLD. The basic building block of a PLD is a logic element that is capable of performing logic functions on a number of input variables. A logic element is typically equipped with circuitry to programmably implement the xe2x80x9csum of productsxe2x80x9d logic or look-up table logic, as well as one or more registers to implement sequential logic. Conventional PLDs combine together large numbers of such logic elements through an array of programmable interconnects to facilitate implementation of complex logic functions. PLDs have found particularly wide application as a result of their combined low up front cost and versatility to the user.
A variety of PLD architectural approaches arranging the interconnect array and logic elements have been developed to optimize logic density and signal routability between the various logic elements. The logic elements are arranged in groups of, for example, eight to form a larger logic array block (xe2x80x9cLABxe2x80x9d). Multiple LABs are arranged in a two dimensional array and are programmably connectable to each other by programmably connecting the inputs and outputs of each LAB to horizontal and vertical interconnect channels.
Continuous advances in semiconductor manufacturing technology have made possible integration of increasingly larger numbers of gates on a chip. Each new generation of PLDs is designed with an appreciably higher logic density. Often the transition to the next generation requires new PLD architectures. One design feature that is subject to reevaluation for new and higher density PLDs is the routing architecture used to interconnect the LABs. There are four types of routing architectures currently being used for a LAB within the PLD: a 1-sided architecture, a 1xc2xd-sided architecture, a 2-sided architecture, and a 4-sided architecture.
FIG. 1 shows the prior art 2-sided architecture, 1xc2xd-sided architecture, and 1-sided architecture. Routing channels are located above, below, to the left, and to the right side of each LAB. The routing channel may run in the horizontal direction (i.e., a horizontal channel) or the vertical direction (i.e., a vertical channel). In the 2-sided routing architecture, a LAB 120 transmits and receives signals to and from a H-channel 123a and a V-channel 126b but does not transmit or receive signals from a V-channel 126a and a H-channel 126b. In the 1xc2xd-sided routing architecture, a LAB 140 transmits and receives signals from a H-channel 143a but only transmits signals to a V-channel 146 and does not transmit or receive signals from a V-channel 146a and a H-channel 143b. In a 1-sided routing architecture, a LAB 160 transmits and receives signals from a H-channel 163a but does not transmit or receive signals from a H-channel 163b, a V-channel 166a and a V-channel 166b. 
FIG. 1 also shows a symmetrical 4-sided architecture where a LAB 100 is coupled to all four of the routing channels. The LAB 100 transmits and receives signals to and from a H-Channel 103a, a H-channel 103b, a V-channel 106a, and a V-channel 106b. Switches (i.e., a switch 110a, a switch 110b, a switch 110c, and a switch 110d) couple the horizontal channels (i.e., a H-channel 103a and a H-channel 103b) with the vertical channels (i.e., a V-channel 106a and a V-channel 106b). The symmetrical 4-sided architecture has characteristics such as that the number of input pins and output pins on all four sides of the LAB are the same. The routing channels (e.g., the horizontal channels and the vertical channels) also have the same widths, e.g., the number of wires in the horizontal channels is the same as the number of wires in the vertical channels. This symmetrical architecture forces the LAB to have a square layout and maintain the square layout as the number of logical elements within the LAB increases. Maintaining the symmetrical number of pins and channel widths may cause inefficiency. For example, the optimum number of logic elements in the LAB may dictate that the LAB not have a square layout with symmetrical characteristics. Also, if redundancy is supported such that a defective row or column of LABs is replaceable, then it would be inefficient to have the same number of routing resources (e.g., multiplexers and drivers) on both the horizontal channels and the vertical channels.
The 2-sided architecture, the 1xc2xd-sided architecture, and the 1-sided architecture can all support redundancy. However, because the number of channels that a LAB within these architectures connect to are fewer than the LAB 100 of the 4-sided architecture, the LAB in the 2-sided architecture, the 1xc2xd-sided architecture, or the 1-sided architecture generally takes a longer time to transmit a signal to another LAB resulting in the PLD having a slower circuit speed (e.g., the delay for the transmitted signal to reach the intended LAB is generally greater in the 2-sided architecture, the 1xc2xd-sided architecture, and the 1-sided architecture than the 4-sided architecture). When a LAB connects to fewer channels, that LAB has fewer number of other LABs that it can connect to using a single routing wire. In general, the fewer the number of other LABs that can be connected to using a single routing wire, the greater the time required to transmit a signal to another LAB. For example, in FIG. 1, using single wires that each can reach another LAB a distance of up to four LABs away, a LAB in the 4-sided architecture can connect to 44 other LABs, however, a LAB in the 1-sided architecture can connect only to 8 other LABs, a LAB in the 1xc2xd-sided architecture can connect only to 12 other LABs, and a LAB in the 2-sided architecture can connect only to 16 other LABs.
For the foregoing reasons, it is desirable to have a routing architecture that maximizes the number of channels to which a particular LAB can connect and may have asymmetric characteristics.
According to an embodiment of the present invention, an integrated circuit is described. The integrated circuit includes a function block that has multiple inputs and multiple outputs. The integrated circuit includes a first channel coupled to a first portion of the multiple inputs located on a first side of the function block and is also coupled to a first portion of the multiple outputs located on the first side of the function block. The integrated circuit also includes a second channel coupled to a second portion of the multiple inputs located on a second side of the function block where the second side is opposite the first side. The second channel is also coupled to a second portion of the multiple outputs located on the second side of the function block.
The integrated circuit includes a third channel coupled to the first channel and the second channel and coupled to a third portion of the multiple inputs located on a third side of the function block and coupled to a third portion of the multiple outputs located on the third side of the function block. The integrated circuit also includes a fourth channel associated with a fourth side of the function block that is opposite the third side. The fourth channel is coupled only to the first channel and the second channel.
Within the integrated circuit, there is at least one of: (a) a difference between any two of a number of inputs of the first, second, or third portion of the multiple inputs, (b) a difference between any two of a number of outputs of the first, second, or third portion of the multiple outputs, and (c) a difference between any two of the number of inputs combined with the number of outputs of the first, second, or third portion of the multiple inputs and outputs.